Semiconductor device having insulated gate field effect transistors and method of manufacturing the same

ABSTRACT

N-type semiconductor region and P-type semiconductor region are provided in a surface region of a semiconductor substrate. Insulating film and silicon containing film are laminated on the semiconductor substrate. P-type impurities are introduced into a first portion of the silicon containing film above the N-type semiconductor region. The first portion of the silicon containing film is thinned in the thickness direction. N-type impurities are introduced into a second portion of the silicon containing film above the P-type semiconductor region. A mask is provided on the silicon containing film. The first and second portions of the silicon containing film are etched together using the mask as an etching mask to form gate electrode films above the N-type and P-type semiconductor regions respectively. P-type and N-type impurities are introduced into the N-type and P-type semiconductor regions to form P-type and N-type source and drain layers.

CROSS REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2007-190800, filed on Jul. 23,2007, the entire contents of which are incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to a semiconductor device having insulatedgate field effect transistors of different conductivity channel typeswhich are formed on a semiconductor substrate, and also relates to amethod of manufacturing the semiconductor device.

DESCRIPTION OF THE BACKGROUND

A CMOS (Complementary Metal Oxide Semiconductor) semiconductor device iswidely used. The CMOS semiconductor device is provided with insulatedgate field effect transistors of different conductivity channel types ona common semiconductor substrate. Gate electrodes of insulated gatefield effect transistors of a CMOS semiconductor device need to havedesired processed shapes, as development of miniaturization, lowervoltage performance and higher integration of the insulated gate fieldeffect transistors.

A method of forming gate electrodes of a CMOS semiconductor device isdiscloses in Japanese Patent Application Publication (Kokai) No.11-17024. The CMOS semiconductor device is provided with N-channel andP-channel insulated gate field effect transistors. The N-channelinsulated gate field effect transistor is provided with an N⁺ gateelectrode of N⁺ polycrystalline silicon in which N-type impurities arecontained in high concentration. The P-channel insulated gate fieldeffect transistor is provided with a P⁺ gate electrode of P⁺polycrystalline silicon in which P-type impurities are contained in highconcentration.

A gate insulating film is formed on a semiconductor substrate to formN-channel and P-channel insulated gate field effect transistors. N⁺ andP⁺ polycrystalline silicon films are formed on the gate insulating film.These N⁺ and P⁺ polycrystalline silicon films are etched and processedat the same time by RIE (Reactive Ion Etching), for example, using anetching mask, so as to form N⁺ and P⁺ gate electrodes.

The gate insulating film under the N⁺ polycrystalline silicon film maybe over-etched or a surface portion of the semiconductor substrate maybe scooped out, because the N⁺ polycrystalline silicon film is etched atan etching rate larger than that of the P+polycrystalline silicon film.Further, the P⁺ gate electrode may have a taper shape by the etchingprocess. As a result, it may be difficult to form N⁺ and P⁺ electrodeswith desired vertically-etched shapes at the same time.

SUMMARY OF THE INVENTION

According to an aspect of the invention, a semiconductor device isprovided, which comprises a semiconductor substrate having a surfaceregion, the surface region being provided with an N-type semiconductorregion and a P-type semiconductor region, a P-channel insulated gatefield effect transistor formed on the N-type semiconductor region, theP-channel insulated gate field effect transistor having a P-type sourcelayer and a P-type drain layer formed apart from each other in theN-type semiconductor region, a first insulating film formed on theN-type semiconductor region, a first gate electrode film formed on thefirst insulating film and located above a region between the P-typesource and drain layers and a second gate electrode film containingsilicon and P-type impurities formed on the first gate electrode film,the first gate electrode film being made of a material different fromthat of the second gate electrode film, and an N-channel insulated gatefield effect transistor formed on the P-type semiconductor region, theN-channel insulated gate field effect transistor having an N-type sourcelayer and an N-type drain layer formed apart from each other in theP-type semiconductor region, a second insulating film formed on theP-type semiconductor region, a third gate electrode film containingsilicon and N-type impurities formed on the second insulating film andlocated above a region between the N-type source and drain layers, thethird gate electrode film being thicker than the second gate electrodefilm.

According to another aspect of the invention, a method of manufacturinga semiconductor device is provided, which comprises providing an N-typesemiconductor region and a P-type semiconductor region in a surfaceregion of a semiconductor substrate, forming an insulating film to be agate insulating film on the semiconductor substrate, forming a siliconcontaining film on the insulating film, introducing P-type impuritiesinto a first portion of the silicon containing film above the N-typesemiconductor region, etching and thinning the first portion of thesilicon containing film in a thickness direction of the first portionand introducing N-type impurities into a second portion of the siliconcontaining film above the P-type semiconductor region, providing anetching mask having first and second patterns on the silicon containingfilm to position the first and second patterns of the etching maskcorresponding to gate electrode patterns above the thinned first andsecond portions of the silicon containing film respectively, and etchingthe thinned first and second portions together to form gate electrodefilms above the N-type and P-type semiconductor regions respectively,introducing P-type impurities into the N-type semiconductor region usingthe gate electrode film located above the N-type semiconductor region asa mask so as to form P-type source and drain layers in the N-typesemiconductor region and introducing N-type impurities into the P-typesemiconductor region using the gate electrode film located above theP-type semiconductor region as a mask so as to form N-type source anddrain layers in the P-type semiconductor region.

According to further another aspect of the invention, a method ofmanufacturing a semiconductor device, which comprises providing anN-type semiconductor region and a P-type semiconductor region in asurface region of a semiconductor substrate, forming an insulating filmto be a gate insulating film on the semiconductor substrate, forming afirst silicon containing film on the insulating film, introducing P-typeimpurities into a first portion of the first silicon containing filmabove the N-type semiconductor region, forming a protection film on thefirst portion of the first silicon containing film selectively, forminga second silicon containing film covering the protection film and asecond portion of the first silicon containing film above the P-typesemiconductor region, polishing and flattening the second siliconcontaining film to leave the second silicon containing film partiallyabove the second portion of the first silicon containing film so as toform a laminated silicon containing film and introducing N-typeimpurities into at least one of the second portion of the first siliconcontaining film and the remaining second silicon containing film,providing an etching mask having first and second patterns correspondingto gate electrode patterns to position the first and second patterns onthe first portion of the first silicon containing film and the laminatedsilicon containing film respectively, and etching the first portion ofthe first silicon containing film and the laminated silicon containingfilm together to form gate electrode films above the N-type and P-typesemiconductor regions respectively, introducing P-type impurities intothe N-type semiconductor region using the gate electrode film locatedabove the N-type semiconductor region as a mask so as to form P-typesource and drain layers in the N-type semiconductor region andintroducing N-type impurities into the P-type semiconductor region usingthe gate electrode film located above the P-type semiconductor region asa mask so as to form N-type source and drain layers in the P-typesemiconductor region.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 to 8 are cross-sectional views showing steps of a firstembodiment of a method of manufacturing a semiconductor device accordingto the present invention.

FIG. 9 is a cross-sectional view showing a first embodiment of asemiconductor device according to the present invention.

FIGS. 10 to 16 are cross-sectional views showing steps of a secondembodiment of a method of manufacturing a semiconductor device accordingto the invention.

FIG. 17 is a cross-sectional view showing a second embodiment of asemiconductor device according to the invention.

FIGS. 18 to 22 are cross-sectional views showing steps of a thirdembodiment of a method of manufacturing a semiconductor device accordingto the invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be described hereinafter withreference to the accompanying drawings.

A first embodiment of a method of manufacturing a semiconductor deviceaccording to the invention will be described with reference to FIGS. 1to 8. FIGS. 1 to 8 are cross-sectional views showing manufacturing stepsof the first embodiment.

As shown in FIG. 1, a semiconductor substrate 1 is prepared. Thesemiconductor substrate 1 is a silicon substrate of P-type. In thesemiconductor substrate 1, an area 60 is defined to form a P-channelinsulated gate field effect transistor (referred to as “P-channel MISFEThereinafter). In the semiconductor substrate 1, an area 61 is alsodefined to form an N-channel insulated gate field effect transistor(referred to as “N-channel MISFET hereinafter).

N-type and P-type well regions 2, 3 are selectively formed in a surfaceregion of the semiconductor substrate 1. The N-type and P-type wellregions 2, 3 serve as N-type and P-type semiconductor regionsrespectively. A shallow trench isolation layer 4 is buried in a regionincluding an adjacent portion of the N-type and P-type well regions 2, 3in the surface region of the semiconductor substrate 1.

An insulating film 7 for a gate insulating film and a polycrystallinesilicon film 21 for a gate electrode are laminated on the semiconductorsubstrate 1. The insulating film 7 may be an oxidized silicon nitridefilm. Instead of the oxidized silicon nitride film, an oxidized siliconnitride/silicon oxide film or a High-K film such as a film containinghafnium, silicon, oxygen and nitrogen may be formed. The polycrystallinesilicon film 21 may be an un-doped polycrystalline silicon film, forexample. The polycrystalline silicon film may be formed by a CVD(Chemical Vapor Deposition) method or PVD (Physical Vapor Deposition)method.

In FIG. 2, after the polycrystalline silicon film 21 is formed, a resistfilm 22 is selectively formed above the area 60 to form the P-channelMISFET using a well-known lithography method. N-type impurities, forexample, phosphorus (P) ions 70 are implanted into the polycrystallinesilicon film 21 above the area 61 to form the N-channel MISFET so thatan N⁺ polycrystalline silicon film is obtained.

As shown in FIG. 3, after the resist film 22 is removed, a resist film22 a is selectively formed above the area 61 to form the N-channelMISFET using a well-known lithography method. The polycrystallinesilicon film 21 above the area 60 is etched by the thickness that ispredetermined below, using a RIE method, for example.

The etching rates of N⁺ and P⁺ polycrystalline silicon films aremeasured to form N-channel and P-channel MISFETs in order to determinethe thickness to etch the polycrystalline silicon film 21. The thicknessto be etched is decided so as to realize that the etching time periodsto reach the etching end points of the N⁺ and P⁺ polycrystalline siliconfilms are substantially same when the etching is started at the sametime, in consideration of the measured etching rates of the N⁺ and P⁺polycrystalline silicon films and the thickness of the polycrystallinesilicon film 21, as is described below.

The following expressions are given to decide the relationship betweenthe thickness T1 of the N⁺ polycrystalline silicon film and thethickness T2 of the P⁺ polycrystalline silicon film. ΔT is equivalent toa compensation thickness to end the etching of the N⁺ and P⁺polycrystalline silicon films at the same time.

T1>T2   (1)

T1−T2=ΔT   (2)

In FIG. 4, P-type impurities, for example, boron (B) ions 71 areimplanted into the polycrystalline silicon film 21 above the area 60,using the resist film 22 a as a mask, so that a P⁺ polycrystallinesilicon film 8 is obtained.

In FIG. 5, after the resist film 22 a is removed, a hard mask 23 isformed on the polycrystalline silicon film 21. The hard mask 23 may beformed by using a CVD method for forming an insulating film such as asilicon-nitride (SiN) film or TEOS film. After the hard mask 23 isformed, a resist film 22 b is selectively formed above regions to formgate electrodes, using a well-known lithography method.

In FIG. 6, the hard mask 23 is etched utilizing a RIE method, forexample, using the resist film 22 b as an etching mask, so as to obtainhard mask patterns 23 a, 23 b.

The RIE method is carried out desirably under the etching condition thatgives the etching rate of the hard mask 23 larger than that of the P⁺and N⁺ polycrystalline silicon films 8, 9 and that shows a large etchingselectivity of the hard mask 23 to the P⁺ and N⁺ polycrystalline siliconfilms 8, 9.

The resist film 22 b is removed. After the removal of the resist film 22b, As shown in FIG. 7, the P⁺ and N⁺ polycrystalline silicon films 8, 9are etched together utilizing a RIE method, for example, using the hardmask patterns 23 a, 23 b as etching masks. As a result, gate electrodefilms 8 a, 9 a are formed simultaneously.

It is desirable that the RIE method is carried out under the etchingcondition which gives the etching rate of the P⁺ and N⁺ polycrystallinesilicon films 8, 9 larger than that of the hard mask patterns 23 a, 23 band which shows a large etching selectivity of the P⁺ and N⁺polycrystalline silicon films 8, 9 to the hard mask patterns 23 a, 23 b.It is preferable to adopt a RIE using hydrogen bromide (HBr) or chlorine(Cl₂) as an etching gas.

Further, as shown in FIG. 8, gate insulating films 7 a, 7 b are formedby etching the insulating film 7 using the gate electrode films 8 a, 9 aas etching masks.

The P⁺ and N⁺ polycrystalline silicon films 8, 9 may be etchedsimultaneously utilizing a RIE method using a resist film, not the hardmask patterns 23 a, 23 b, as an etching mask.

In FIG. 8, high-concentration P type impurities, for example, boron (B)ions are implanted using the gate electrode film 8 a of P⁺polycrystalline silicon as a mask to obtain P-type source and drainlayers 5 a, 5 b. High-concentration N type impurities, for example,phosphorus (P) ions are implanted using the gate electrode film 9 a ofN⁺ polycrystalline silicon as a mask to obtain N-type source and drainlayers 6 a, 6 b. The P-type source and drain layers 5 a, 5 b are apartfrom each other. The N-type source and drain layers 6 a, 6 b are apartfrom each other.

The region between the source and drain layers 5 a, 5 b is a firstchannel region. The region between the source and drain layers 6 a, 6 bis a second channel region. The source and drain layers 5 a, 5 b, 6 aand 6 b are shallower than the shallow trench isolation layer 4.

The side surfaces of the laminated films that are composed of the gateinsulating film 7 a, the gate electrode film 8 a and the hard maskpattern 23 a are covered with a side-wall insulating film 11 a. The sidesurfaces of the laminated films that are composed of the gate insulatingfilm 7 b, the gate electrode film 9 a and the hard mask pattern 23 b arecovered with a side-wall insulating film 11 b.

The hard mask patterns 23 a, 23 b are removed so that the surfaces ofthe gate electrode films 8 a, 9 a are exposed. Further, an interlayerinsulating film 12 is formed to cover the entire surface of thesemiconductor substrate 1.

Contact holes 13 a to 13 d are formed in the interlayer insulating film12 to expose portions of the source and drain layers 5 a, 5 b and 6 a, 6b. Further, first-layer interconnections 14 a to 14 d are formed to burythe contact holes 13 a to 13 d.

By the above steps, a P-channel MISFET 62 is formed on the N-type wellregion 2. An N-channel MISFET 63 is formed on the P-type well region 3.The P-channel MISFET 62 and the N-channel MISFET 63 form a semiconductordevice 50.

In the above described manufacturing method, the side-wall insulatingfilms 11 a and the source and drain layers 5 a, 5 b of the P-channelMISFET 62 may be formed after low-concentration P-type diffusion layers,which are apart from each other in a channel direction and which arecalled as “extension regions”, are formed in the surface region of theN-type well region 2.

The side-wall insulating films 11 b and the source and drain layers 6 a,6 b of the N-channel MISFET 63 may be formed after low-concentrationN-type diffusion layers, which are apart from each other in a channeldirection and which are called as “extension regions”, are formed in thesurface region of the P-type well region 3.

According to the manufacturing method of the embodiment described above,the thickness of the P⁺ polycrystalline silicon film 8, which will beused as the gate electrode 8 a of the P-channel MISFET 62, is formed tobe thinner than that of the N⁺ polycrystalline silicon film 9 to be thegate electrode 9 a of the N-channel MISFET 63 by the compensationthickness. By the step, the times to reach the etching end points of theN⁺ and P⁺ polycrystalline silicon films become substantially same whenthe etching is started at the same time.

As a result, substantially vertical processed shapes may be obtained forthe gate electrodes 8 a, 9 a respectively. The insulating film 7 for thegate insulating films may be suppressed to be over-etched so that thesurface portion of the semiconductor substrate 1 may be prevented frombeing scooped out.

In the embodiment, the polycrystalline silicon film 21 is employed toform the gate electrodes. Instead, an amorphous silicon film or asilicon germanium (SiGe) film may be used. The NO film is employed forthe gate insulating film 7 a, 7 b to form Metal-Insulator-Semiconductorfield effect transistors (MISFETs). Instead, a silicon thermal-oxidationfilm may be used to form Metal-Oxide-Semiconductor field effecttransistors (MOSFETs).

In the above embodiment, the N⁺ polycrystalline silicon film 9 is formedprior to the P⁺ polycrystalline silicon film 8. However, the P⁺polycrystalline silicon film 8 may be formed prior to the N⁺polycrystalline silicon film 9. Before P-type and N-type impurities aredoped into the polycrystalline silicon film 21, the polycrystallinesilicon film 21 may be etched in the thickness direction, above the area60 to form the P-channel MISFET.

In more detail, a resist film may be provided on the polycrystallinesilicon film 21 above the area 61 to form the N-channel MISFET. Usingthe resist film as a mask, the polycrystalline silicon film 21 may beetched to be thinner above the area 60. Further, utilizing the resistfilm as a mask, P-type impurities may be doped into the polycrystallinesilicon film 21 above the area 60.

A first embodiment of a semiconductor device according to the inventionwill be described with reference to FIG. 9. FIG. 9 is a cross-sectionalview showing the semiconductor device of the first embodiment. In FIG.9, the same portions as those in FIGS. 1 to 8 are designated by the samereference numerals.

As shown in FIG. 9, N-type and P-type well regions 2, 3 are selectivelyformed in a surface region of a semiconductor substrate 1. P⁺ source anddrain layers 5 a, 5 b are selectively formed in a surface region of theN-type well region 2. N⁺ source and drain layers 6 a, 6 b areselectively formed in a surface region of the P-type well region 3.

A shallow trench isolation layer 4 is formed in the surface region ofthe semiconductor substrate 1. The shallow trench isolation layer 4isolates P-channel and N-channel MISFETs 62 a, 63 a. The shallow trenchisolation layer 4 is buried more deeply than the P⁺ source and drainlayers 5 a, 5 b and the N⁺ source and drain layers 6 a, 6 b.

A gate insulating film 7 a, a lower gate electrode film 33 a and anupper gate electrode film 32 a are laminated on a region between the P⁺source and drain layers 5 a, 5 b. These laminated films overlap the P⁺source and drain layers 5 a, 5 b partially. A gate insulating film 7 b,a lower gate electrode film 31 b and an upper gate electrode film 32 bare laminated on a region between the N⁺ source and drain layers 6 a, 6b. These laminated films overlap the N⁺ source and drain layers 6 a, 6 bpartially.

The P⁺ source and drain layers 5 a, 5 b, the gate insulating film 7 a,the lower gate electrode film 33 a and the upper gate electrode film 32a form the P-channel MISFET 62 a. The N⁺ source and drain layers 6 a, 6b, the gate insulating film 7 b, the lower gate electrode film 31 b andthe upper gate electrode film 32 b form the N-channel MISFET 63 a. TheP-channel and N-channel MISFET 62 a, 63 a form a semiconductor device 50a.

The side surfaces of the laminated films that are composed of the gateinsulating film 7 a and the lower and upper gate electrode film 33 a, 32a are covered with a side-wall insulating film 11 a.

The side surfaces of the laminated films that are composed of theinsulating film 7 b and the lower and upper gate electrode film 31 b, 32b are covered with a side-wall insulating film 11 b. An interlayerinsulating film 12 is formed to cover the semiconductor substrate 1, theshallow trench isolation layer 4 and the side-wall insulating film 11 a,11 b.

Contact holes 13 a to 13 d are formed in the interlayer insulating film12 to expose portions of the source and drain layers 5 a, 5 b and 6 a, 6b. First-layer Interconnections 14 a to 14 d are formed to bury thecontact holes 13 a to 13 d.

In the embodiment, tungsten nitride (WN) is used for the lower gateelectrode film 33 a above an area 60 of the semiconductor substrate 1 toform the P-channel MISFET 62 a. Instead, tungsten (W), tungsten silicide(WSi), tungsten carbide (WC) and so forth may be used. Moreover, nickel(nickel), palladium (Pd), platinum (Pt), cobalt (Co), ruthenium (Ru) orrhodium (Rh) may be used which is a metal having a work function nearthat of a P⁺ polycrystalline silicon film. Further, nitride, silicide orcarbide of each of the metals may be employed.

In the embodiment, titanium nitride (TiN) is used for the lower gateelectrode film 31 b above an area 61 of the semiconductor substrate 1 toform the N-channel MISFET 62 a. Instead, titanium (Ti), titaniumsilicide (TiSi) or titanium carbide (TiC) may be used. Moreover,zirconium (Zr), hafnium (Hf), vanadium (V), tantalum (Ta), chromium(Cr), or molybdenum (Mo) may be used which is a metal having a workfunction near that of a N⁺ polycrystalline silicon film. Further,nitride, silicide or carbide of each of the metals may be employed.

The lower gate electrode film 33 a, 31 b have the same thicknessapproximately and take the same etching time substantially to etch in athickness direction.

A P⁺ polycrystalline silicon film doped with high concentration P-typeimpurities is used for the upper gate electrode film 32 a. An N⁺polycrystalline silicon film doped with high concentration N-typeimpurities is used for the upper gate electrode film 32 b.

When a high temperature heat treatment is necessary after the lower gateelectrode film 33 a, 31 b are formed, barrier metal film are formeddesirably between the lower gate electrode film 33 a, 31 b and thesecond gate electrode film 32 a, 32 b respectively to suppress producingsilicide.

The following expressions are given to show the relationship between thethickness T2 a of the upper gate electrode film 32 a and the thicknessT1 a of the upper gate electrode film 32 b.

T1a>T2a   (3)

T1a−T2a=ΔTa   (4)

The etching rate of the upper gate electrode film 32 a is smaller thanthat of the upper gate electrode film 32 b. The compensation thicknessΔTa is determined so as to end etching tungsten nitride and titaniumnitride films to form the lower gate electrode films 33 a, 31 brespectively, which are disposed under P⁺ and N⁺ polycrystalline siliconfilms to form the upper gate electrode films 31 b, 32 b, at the sametime substantially, when the laminated tungsten nitride film and P⁺polycrystalline silicon film and the laminated titanium nitride film andN⁺ polycrystalline silicon film starte to be etched simultaneously andvertically (in a thickness direction) by a RIE processing.

According to the embodiment described above, the P⁺ polycrystallinesilicon film to form the upper gate electrode 32 a of the P-channelMISFET 62 a is formed to be thinner than the N⁺ polycrystalline siliconfilm to form the upper gate electrode 32 b of the N-channel MISFET 63 aby the compensation thickness ΔTa. As a result, the times to reach theetching end points of the P⁺ and N⁺ polycrystalline silicon films (orthe tungsten nitride and titanium nitride films) are substantially samewhen the etching processing is started at the same time.

Accordingly, substantially vertical processed shapes may be obtained forthe laminated lower and upper gate electrodes 33 a, 32 a and thelaminated lower and upper gate electrodes 31 b, 32 b. The insulatingfilm to be the gate insulating film 7 a, 7 b may be suppressed to beover-etched so that the surface portion of the semiconductor substrate 1may be prevented from being scooped out.

In the embodiment, the upper gate electrode film 32 a of P⁺polycrystalline silicon is formed on the lower gate electrode film oftungsten nitride which is formed on the gate insulating film 7 a.Further, the upper gate electrode film 32 b of N⁺ polycrystallinesilicon is formed on the lower gate electrode film of titanium nitridewhich is formed on the gate insulating film 7 b. According to thestructures, deterioration of driving capability of the P-channel andN-channel MISFET 62 a, 63 a may be suppressed which is caused byincrease in appearance of the thickness of the gate insulating films dueto enhancement of gate depletion, in comparison with the case that theP⁺ and N⁺ polycrystalline silicon films 32 a, 32 b are formed directlyon the gate insulating film 7 a, 7 b respectively. In addition, theboron (B) contained in the P⁺ polycrystalline silicon film may besuppressed to permeate so that the threshold voltage (Vth) of theP-channel MISFET 62 a may be suppressed to change.

A second embodiment of a method of manufacturing a semiconductor deviceaccording to the invention will be described with reference to FIGS. 10to 16. The manufacturing method of the second embodiment is a method ofmanufacturing the semiconductor device 50 a which has been explainedwith reference to FIG. 9. FIGS. 10 to 16 are cross-sectional viewsshowing manufacturing steps of the second embodiment. In FIGS. 10 to 16,the same portions as those in FIGS. 1 to 8 are designated by the samereference numerals.

As shown in FIG. 10, a semiconductor substrate 1 of P-type silicon isprepared. N-type and P-type well regions 2, 3 are selectively formed ina surface region of the semiconductor substrate 1. A shallow trenchisolation layer 4 is buried in a region including an adjacent portion ofthe N-type and P-type well regions 2, 3. An insulating film 7 is formedto serve as a gate insulating film.

A titanium nitride film (TiN) 31 is laminated on the insulating film 7to form a lower gate electrode film 31 b of FIG. 9. The titanium nitridefilm 31 is formed by a sputtering method. After the titanium nitridefilm 31 is formed, a resist film 22 c is selectively formed on the area61 to form an N-channel MISFET using a well-known lithography method. Aportion of the titanium nitride film 31, that is located above the area60 to form a P-channel MISFET, is removed by using the resist film 22 cas an etching mask. It is desirable to employ the combination of dry andwet etching or wet etching to avoid causing damage to the insulatingfilm 7.

In FIG. 11, after removing the resist film 22 c, a tungsten nitride (WN)film 33 to be a lower gate electrode film 33 a is formed. The tungstennitride film 33 is formed by a sputtering method. After the tungstennitride film 33 is formed, a resist film 22 d is selectively formedabove the area 60 to form a P-channel MISFET using a well-knownlithography method. A portion of the tungsten nitride film 33, that islocated above the area 61 to form an N-channel MISFET, is removed byusing the resist film 22 d as an etching mask.

In FIG. 12, after removing the resist film 22 d, an un-dopedpolycrystalline silicon film 21 a is formed on the titanium nitride film31 and the tungsten nitride film 33. The polycrystalline silicon film 21a may be formed by a CVD method or PVD method. In place of the un-dopedpolycrystalline silicon film 21 a, an amorphous silicon film or apolycrystalline silicon germanium (SiGe) film may be used.

In FIG. 13, a resist film 22 e is selectively formed on the area 60 toform the P-channel MISFET using a well-known lithography method. N-typeimpurities, for example, phosphorus (P) ions 70 are implanted into thepolycrystalline silicon film 21 a above the area 61 to form theN-channel MISFET so that an N⁺ polycrystalline silicon film 32 b isobtained.

As shown in FIG. 14, after the resist film 22 e is removed, a resistfilm 22 f is selectively formed on the N⁺ polycrystalline silicon film32 b above the area 61 to form the N-channel MISFET using a well-knownlithography method. A portion of the polycrystalline silicon film 21 a,which is located above the area 60 to form the P-channel MISFET, isetched by a predetermined thickness using a RIE method, for example.

The etching rates of a titanium nitride film and an N⁺ polycrystallinesilicon film and those of a tungsten nitride film and a P⁺polycrystalline silicon film are measured in order to decide thethickness to etch the portion of the polycrystalline silicon film 21 a.It is desirable that the thickness to be etched is decided so as torealize that the times to reach the etching end points of the titaniumnitride and tungsten nitride films are substantially same when theetching is started at the same time, in consideration of the measuredetching rates of the titanium nitride film, the tungsten nitride filmand the N⁺ and P⁺ polycrystalline silicon films and of the thicknessesof these films.

The difference between the thickness T1 a of the N⁺ polycrystallinesilicon film and the thickness T2 a of the P⁺ polycrystalline siliconfilm is equivalent to a compensation thickness ΔTa as shown in FIG. 9.

In FIG. 14, P-type impurities, for example, boron (B) ions 71 areimplanted into the polycrystalline silicon film 21 a above the area 60,using the resist film 22 f as a mask, so as to form a P⁺ polycrystallinesilicon film 32 a to obtain a second gate electrode film.

In FIG. 15, after the resist film 22 f is removed, a hard mask 23 of asilicon-nitride (SiN) film is formed on the P⁺ polycrystalline siliconfilm 32 a and the N⁺ polycrystalline silicon film 32 b. The hard mask 23may be formed by using a CVD method. In place of a silicon-nitride film,an insulating film such as a TEOS film may be used. After the hard mask23 is formed, the impurities contained in the P⁺ polycrystalline siliconfilm 32 a and the N⁺ polycrystalline silicon film 32 b are diffusedthermally to obtain a uniform impurity concentration of the P⁺polycrystalline silicon film 32 a and the N⁺ polycrystalline siliconfilm 32 b.

In FIG. 16, a resist film 22 g is selectively formed above regions wheregates will be formed, using a well-known lithography method. The hardmask 23 is etched utilizing a RIE method, for example, using the resistfilm 22 g as an etching mask, so that hard mask patterns are formed. Itis desirable that the RIE method is carried out under the etchingcondition that gives the etching rate of the hard mask 23 larger thanthat of the P⁺ and N⁺ polycrystalline silicon films 32 a, 32 b and thatshows a large etching selectivity of the hard mask 23 to the P⁺ and N⁺polycrystalline silicon films 32 a, 32 b.

The resist film 22 g are removed. After the removal of the resist film22 g, the laminated titanium nitride film 31 and N⁺ polycrystallinesilicon film 32 b above the area 61 and the laminated tungsten nitridefilm 33 and P⁺ polycrystalline silicon film 32 a above the area 60 startto be etched simultaneously utilizing a RIE method, for example, usingthe hard mask patterns as etching masks. As a result, lower gateelectrode films 33 a, 31 b and upper gate electrode films 32 a, 32 b areformed as shown in FIG. 9.

The RIE method is carried out desirably under the etching condition thatgives the etching rate of the P⁺ and N⁺ polycrystalline silicon films 32a, 32 b and the titanium nitride and tungsten nitride films 31, 33larger than those of the hard mask patterns and that shows a largeetching selectivity between the hard mask patterns and the P⁺ and N⁺polycrystalline silicon films 32 a, 32 b and the titanium nitride andtungsten nitride films 31, 33. It is preferable to adopt a RIE usinghydrogen bromide (HBr) or chlorine (Cl₂) as an etching gas.

Gate insulating films 7 a, 7 b of FIG. 9 are formed by etching theinsulating film 7 using the upper gate electrode films 32 a, 32 b as anetching mask. P-type source and drain layers 5 a, 5 b, N-type source anddrain layers 6 a, 6 b and side-wall insulating film 11 a, 11 b areformed as the manufacturing method of the first embodiment. The hardmask patterns are removed.

Further, an interlayer insulating film 12 is formed, and Contact holes13 a to 13 d are formed in the interlayer insulating film 12 to exposeportions of the source and drain layers 5 a, 5 b and 6 a, 6 b.First-layer Interconnections 14 a to 14 d are formed to bury the contactholes 13 a to 13 d.

According to the manufacturing method of the second embodiment, thethickness of the portion of the polycrystalline silicon film 21 a to bethe P⁺ polycrystalline silicon film 32 a is formed to be thinner thanthat to be the N⁺ polycrystalline silicon film 32 b by the compensationthickness ΔTa. Accordingly, the times to reach the etching end points ofthe titanium nitride film 31 and the tungsten nitride film 33 aresubstantially same.

As a result, substantially vertical processed shapes may be obtained forthe gate electrodes 8 a, 9 a. The insulating film 7 to be the gateinsulating film may be suppressed to be over-etched so that the surfaceportion of the semiconductor substrate 1 may be prevented from beingscooped out.

A second embodiment of a semiconductor device according to the inventionwill be described with reference to FIG. 17. FIG. 17 is across-sectional view showing the semiconductor device of the secondembodiment. In FIG. 17, the same portions as those in FIG. 9 aredesignated by the same reference numerals.

As shown in FIG. 17, N-type and P-type well regions 2, 3, P⁺ source anddrain layers 5 a, 5 b, N⁺ source and drain layers 6 a, 6 b and a shallowtrench isolation layer 4 are selectively formed in a surface region of asemiconductor substrate 1, as the semiconductor device 50 a shown inFIG. 9.

A gate insulating film 7 a, a first gate electrode film 33 a and asecond gate electrode film 34 a are laminated on a region between the P⁺source and drain layers 5 a, 5 b in the semiconductor substrate 1. Theselaminated films overlap the P⁺ source and drain layers 5 a, 5 bpartially.

A gate insulating film 7 b and a third gate electrode film 41 arelaminated on a region between the N⁺ source and drain layers 6 a, 6 b.These laminated films overlap the N⁺ source and drain layers 6 a, 6 bpartially.

The P⁺ source and drain layers 5 a, 5 b, the gate insulating film 7 a,the first gate electrode film 33 a and the second gate electrode film 34a form a P-channel MISFET 62 a. The N⁺ source and drain layers 6 a, 6 b,the gate insulating film 7 b and the third gate electrode film 41 forman N-channel MISFET 63 b. The P-channel and N-channel MISFET 62 a, 63 bform a semiconductor device 50 b.

The side surfaces of the laminated films that are composed of the gateinsulating film 7 a and the first and second gate electrode film 33 a,34 a are covered with a side-wall insulating film 11 a.

The side surfaces of the laminated films that are composed of the gateinsulating film 7 b and the third gate electrode film 41 are coveredwith a side-wall insulating film 11 b. Structures of the other portionsof the semiconductor device 50 b are same as those of the semiconductordevice 50 a shown in FIG. 9.

A tungsten nitride (WN) film is used for the first gate electrode film33 a. A P⁺ polycrystalline silicon film doped with high concentrationP-type impurities is used for the second gate electrode film 34 a. An N⁺polycrystalline silicon film doped with high concentration N-typeimpurities is used for the third gate electrode film 41. Thesemiconductor device according to the second embodiment is manufacturedby the steps of the second embodiment as to the method of manufacturingthe semiconductor device shown in FIGS. 10 to 16, with the step offorming the titanium nitride film excluded.

The following expressions are given to show the relationship between thethickness T1 b of the third gate electrode film 41 and the thickness T2b of the second gate electrode film 34 a.

T1b>T2b   (5)

T1b−T2b=ΔTb   (6)

The etching rate of the second gate electrode film 34 a is smaller thanthat of the third gate electrode film 41. The second gate electrode film34 a is thinner than the third gate electrode film 41 by thecompensation thickness ΔTb. The compensation thickness ΔTb is determinedso that the etching time of the laminated films of the first and secondgate electrode film 33 a, 34 a above the area 60 may be substantiallysame as that of the third gate film 41 above the area 61, when thelaminated films and the third gate electrode film 41 are start to beetched simultaneously and vertically (in a thickness direction) by a RIEprocessing.

The etching ending times are substantially same to reach the etching endpoints of the tungsten nitride film and the N⁺ polycrystalline siliconfilm, when the laminated films of the P⁺ polycrystalline silicon filmand the tungsten nitride film and the N⁺ polycrystalline silicon filmstart to be etched at the same time.

Accordingly, vertically processed shapes may be obtained for thelaminated films and the N⁺ polycrystalline silicon film. An insulatingfilm to form the gate insulating film 7 a, 7 b may be suppressed to beover-etched so that the surface portion of the semiconductor substrate 1may be prevented from being scooped out.

According to the semiconductor device of the second embodiment, thesecond gate electrode 34 a of P⁺ polycrystalline silicon is formed onthe first gate electrode 33 a of metal nitride, for example, tungstennitride above the gate insulating film 7 a of the P-channel MISFET 62 a.

Thus, deterioration of driving capability of the P-channel MISFET 62 amay be suppressed which is caused by increase in appearance of thethickness of the gate insulating film due to enhancement of gatedepletion, in comparison with the case that the P⁺ polycrystallinesilicon films 34 a is formed directly on the gate insulating film 7 a.

In addition, the boron (B) contained in the P⁺ polycrystalline siliconfilm may be suppressed to permeate so that the threshold voltage (Vth)of the P-channel MISFET 62 a may be suppressed to change.

The N-channel MISFET 63 b shows small change of the threshold voltage incomparison with a P-channel MISFET 62 a, because the N-channel MISFET 63b do not cause the problem of permeation phenomenon of boron.

A third embodiment of a method of manufacturing a semiconductor deviceaccording to the invention will be described with reference to FIGS. 18to 22. FIGS. 18 to 22 are cross-sectional views showing manufacturingsteps of the third embodiment.

In FIGS. 18 to 22, the same portions as those in FIGS. 1 to 8 aredesignated by the same reference numerals.

As shown in FIG. 18, a semiconductor substrate 1 is prepared. Thesemiconductor substrate 1 is a silicon substrate of P-type. An N-typewell region 2 and a P-type well region 3 are selectively formed in asurface region of the semiconductor substrate 1. A shallow trenchisolation layer 4 is buried in a region including an adjacent portion ofthe N-type and P-type well regions 2, 3 which is defined in the surfaceregion of the semiconductor substrate 1. An insulating film 7 for a gateinsulating film is formed on the semiconductor substrate 1.

A polycrystalline silicon film 21 b is formed on the insulating film 7.The polycrystalline silicon film 21 b is thinner than thepolycrystalline silicon film 21 formed in the manufacturing method ofthe first embodiment. After the polycrystalline silicon film 21 b isformed, a resist film 22 i is selectively formed on the area 61 to forman N-channel MISFET using a well-known lithography method. P-typeimpurities, for example, boron (B) ions 71 are implanted into a portionof the polycrystalline silicon film 21 b above the area 60 to form aP-channel MISFET using resist film 22 i as a mask so that an P⁺polycrystalline silicon film 80 is obtained as shown in FIG. 19.

In FIG. 19, after the resist film 22 i is removed, a protection film 24is formed on the polycrystalline silicon film 21 b. The protection film24 serves as a mask material to flatten a polycrystalline silicon filmin a CMP (Chemical Mechanical Polishing) method which will be describedbelow. The protection film 24 has a polishing speed smaller than thepolycrystalline silicon film. The protection film 24 is an insulatingfilm such as a silicon nitride film desirably.

The thickness of the protection film 24 is equivalent to thecompensation thickness ΔT described in the manufacturing method of thefirst embodiment desirably. After the protection film 24 is formed, sresist film 22 j is selectively formed above the area 60 to form theP-channel MISFET using a well-known lithography method.

In FIG. 20, a portion of the surface of the polycrystalline silicon film21 b is exposed above the area 61 to form the N-channel MISFET byetching the protection film 24 using resist film 22 j as a mask. N-typeimpurities, for example, phosphorus (P) ions 70 are implanted into thepolycrystalline silicon film 21 b above the area 61, using the resistfilm 22 j as a mask, so as to form the N-channel MISFET. As a result, anN⁺ polycrystalline silicon film 81 is obtained to be a gate electrodefilm. The resist film 22 j is removed.

In FIG. 21, after the resist film 22 j is removed, an N⁺ polycrystallinesilicon film 21 c is formed by using a CVD method, for example, on theprotection film 24 and the N⁺ polycrystalline silicon film 21 b. Thethickness of the N⁺ polycrystalline silicon film 21 c is thicker thanthe thickness equivalent to the compensation thickness ΔT described inthe manufacturing method of the first embodiment desirably.

An un-doped polycrystalline silicon film may be used in place of the N⁺polycrystalline silicon film 21 c. When the N⁺ polycrystalline siliconfilm 21 c is used, the ion-implantation of the N-type impurities shownin FIG. 20 may be omitted. It may be sufficient that at least one of aportion of the polycrystalline silicon film 21 b and a portion of thepolycrystalline silicon film 21 c respectively above the area 61 isdoped with N-type impurities.

The polycrystalline silicon film 21 c is flattened to the degree toexpose the surface of the protection film 24 utilizing a CMP method.After the flattening, the protection film 24 is removed.

In FIG. 22, the polycrystalline silicon film 21 c will remain on the N⁺polycrystalline silicon film 81 selectively. The thickness of thepolycrystalline silicon film 21 c may be equivalent to the compensationthickness ΔT as described in the manufacturing method of the firstembodiment. The remaining portion of the polycrystalline silicon film 21c forms a gate electrode of the N-channel MISFET together with the N⁺polycrystalline silicon film 81.

When the protection film 24 is a silicon nitride (SiN) film, thermalphosphoric acid is desirably used to remove the protection film 24. Adry etching may also be used in the condition that the etching rate ofthe silicon nitride film is larger than that of a polycrystallinesilicon film and that a large etching selectivity is shown between thesilicon nitride film and the polycrystalline silicon film. When theprotection film 24 is an insulating film other than a silicon nitridefilm, a wet etching is desirably used which etches the polycrystallinesilicon film hardly.

A hard mask is formed on the P⁺ polycrystalline silicon film 80 and thepolycrystalline silicon film 21 as shown in the step of FIG. 5 of themanufacturing method of the first embodiment. Impurities contained inthe P⁺ polycrystalline silicon film 80 and those contained in the N⁺polycrystalline silicon film 81, 21 c are diffused thermally to uniformthe impurity concentrations respectively. The hard mask is etchedselectively to form hard mask patterns corresponding to gate electrodes.

The P⁺ polycrystalline silicon film 80 and the laminated films of the N⁺polycrystalline silicon films 81, 21 c are selectively etchedsimultaneously utilizing a RIE method, for example, using the hard maskpatterns as etching masks. As a result, gate electrode films are formedabove the areas 60, 61 to form the P-channel and N-channel MISFETs. Thesubsequent steps are same as those of the manufacturing method of thefirst embodiment.

In the embodiment, the thickness of the P⁺ polycrystalline silicon film80 is formed to be thinner than that of the laminated films by thecompensation thickness ΔT as the manufacturing method of the firstembodiment. Thus, the times to reach the etching end points of the P⁺polycrystalline silicon film 80 and the laminated films aresubstantially same when the etching starts at the same time.

As a result, vertical processing shapes may be obtained for the gateelectrodes. The insulating film 7 to be the gate insulating film may besuppressed to be over-etched so that the surface portion of thesemiconductor substrate 1 may be prevented from being scooped out.

A titanium nitride film and a tungsten nitride film may be formed afterthe insulating film 7 is formed and before the polycrystalline siliconfilm 21 b is formed, as the titanium nitride film 31 and the tungstennitride film 33 shown in FIGS. 10 to 12.

In the above-mentioned embodiment, the N⁺ polycrystalline silicon filmsare used for the most upper gate electrode films of the N-channelMISFETs respectively. The P⁺ polycrystalline silicon films are used forthe most upper gate electrode films of the P-channel MISFETsrespectively.

In order to lower the gate resistances of the P-channel and N-channelMISFETs, metal silicide films may be selectively formed on the gateelectrode films respectively. Portions of the P⁺ and N⁺ polycrystallinesilicon films may be silicide to lower the gate resistances.

Other embodiments or modifications of the present invention will beapparent to those skilled in the art from consideration of thespecification and practice of the invention disclosed herein. It isintended that the specification and embodiments be considered asexemplary only, with a true scope and spirit of the invention beingindicated by the following.

1.-9. (canceled)
 10. A method of manufacturing a semiconductor device,comprising: providing an N-type semiconductor region and a P-typesemiconductor region in a surface region of a semiconductor substrate;forming an insulating film to be a gate insulating film on thesemiconductor substrate; forming a silicon containing film on theinsulating film; introducing P-type impurities into a first portion ofthe silicon containing film above the N-type semiconductor region,etching and thinning the first portion of the silicon containing film ina thickness direction of the first portion and introducing N-typeimpurities into a second portion of the silicon containing film abovethe P-type semiconductor region; providing an etching mask having firstand second patterns on the silicon containing film to position the firstand second patterns of the etching mask corresponding to gate electrodepatterns above the thinned first and second portions of the siliconcontaining film respectively, and etching the thinned first and secondportions together to form gate electrode films above the N-type andP-type semiconductor regions respectively; introducing P-type impuritiesinto the N-type semiconductor region using the gate electrode filmlocated above the N-type semiconductor region as a mask so as to formP-type source and drain layers in the N-type semiconductor region andintroducing N-type impurities into the P-type semiconductor region usingthe gate electrode film located above the P-type semiconductor region asa mask so as to form N-type source and drain layers in the P-typesemiconductor region.
 11. A method of manufacturing a semiconductordevice, according to claim 10, wherein etching of the thinned firstportion and the second portion of the silicon containing film and to beetched in the thickness direction is ended in the same time periodsubstantially in forming the gate electrode films.
 12. A method ofmanufacturing a semiconductor device according to claim 10, furthercomprising: forming a first conductive film on the insulating film abovethe N-type semiconductor region after the insulating film is formed andbefore the silicon containing film is formed, the first conductive filmbeing composed of a material different from that of the siliconcontaining film and being etched together with the thinned first portionof the silicon containing film to be processed to form the gateelectrode film above the N-type semiconductor region.
 13. A method ofmanufacturing a semiconductor device according to claim 12, furthercomprising: forming a second conductive film on the insulating filmabove the P-type semiconductor region after the insulating film isformed and before the silicon containing film is formed, the secondconductive film being composed of a material different from that of thesilicon containing film and being etched together with the secondportion of the silicon containing film to be processed to form the gateelectrode film above the P-type semiconductor region.
 14. A method ofmanufacturing a semiconductor device according to claim 13, wherein thefirst and second conductive films are a film composed of at least oneselected from a metal film, a metal nitride film, a metal silicide filmor a metal carbide film.
 15. A method of manufacturing a semiconductordevice according to claim 14, wherein the first and second conductivefilms are composed of different materials.
 16. A method of manufacturinga semiconductor device according to claim 14, wherein the first andsecond conductive films have the same thickness approximately.
 17. Amethod of manufacturing a semiconductor device, comprising: providing anN-type semiconductor region and a P-type semiconductor region in asurface region of a semiconductor substrate; forming an insulating filmto be a gate insulating film on the semiconductor substrate; forming afirst silicon containing film on the insulating film; introducing P-typeimpurities into a first portion of the first silicon containing filmabove the N-type semiconductor region, forming a protection film on thefirst portion of the first silicon containing film selectively, forminga second silicon containing film covering the protection film and asecond portion of the first silicon containing film above the P-typesemiconductor region, polishing and flattening the second siliconcontaining film to leave the second silicon containing film partiallyabove the second portion of the first silicon containing film so as toform a laminated silicon containing film and introducing N-typeimpurities into at least one of the second portion of the first siliconcontaining film and the remaining second silicon containing film;providing an etching mask having first and second patterns correspondingto gate electrode patterns to position the first and second patterns onthe first portion of the first silicon containing film and the laminatedsilicon containing film respectively, and etching the first portion ofthe first silicon containing film and the laminated silicon containingfilm together to form gate electrode films above the N-type and P-typesemiconductor regions respectively; introducing P-type impurities intothe N-type semiconductor region using the gate electrode film locatedabove the N-type semiconductor region as a mask so as to form P-typesource and drain layers in the N-type semiconductor region andintroducing N-type impurities into the P-type semiconductor region usingthe gate electrode film located above the P-type semiconductor region asa mask so as to form N-type source and drain layers in the P-typesemiconductor region.
 18. A method of manufacturing a semiconductordevice, according to claim 17, wherein etching of the first portion ofthe silicon containing film and the laminated silicon containing film inthe thickness direction is ended in the same time period substantiallyin forming the gate electrode films.
 19. A method of manufacturing asemiconductor device according to claim 17, further comprising: forminga first conductive film on the insulating film above the N-typesemiconductor region after the insulating film is formed and before thefirst silicon containing film is formed, the first conductive film beingcomposed of a material different from that of the first siliconcontaining film and being etched together with the first portion of thefirst silicon containing film to be processed to form the gate electrodefilm above the N-type semiconductor region.
 20. A method ofmanufacturing a semiconductor device according to claim 17, furthercomprising: forming a second conductive film on the insulating filmabove the P-type semiconductor region after the insulating film isformed and before the first silicon containing film is formed, thesecond conductive film being composed of a material different from thatof the first silicon containing film and being etched together with thelaminated silicon containing film to be processed to form the gateelectrode film above the P-type semiconductor region.